1. Field of the Invention
The present invention relates generally to technology for programming memory devices.
2. Description of the Related Art
Semiconductor memory devices have become more popular for use in various electronic devices. For example, non-volatile semiconductor memory is used in cellular telephones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices and other devices. Electrical Erasable Programmable Read Only Memory (EEPROM) and flash memory are among the most popular non-volatile semiconductor memories.
Typical EEPROMs and flash memories utilize a memory cell with a floating gate that is provided above and insulated from a channel region in a semiconductor substrate. The channel region is positioned in a p-well between source and drain regions. A control gate is provided over and insulated from the floating gate. The threshold voltage of the memory is controlled by the amount of charge that is retained on the floating gate. That is, the level of charge on the floating gate determines the minimum amount of voltage that must be applied to the control gate before the memory cell is turned on to permit conduction between its source and drain.
Some EEPROM and flash memory devices have a floating gate that is used to store two ranges of charges and, therefore, the memory cell can be programmed/erased between two states. When programming an EEPROM or flash memory device, a program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised.
Typically, the program voltage applied to the control gate is applied as a series of pulses. The magnitude of the pulses is increased with each successive pulse by a predetermined step size (e.g. 0.2 v). In the periods between the pulses, verify operations are carried out. That is, the programming level of each cell of a group of cells being programmed in parallel is read between each programming pulse to determine whether it is equal to or greater than a verify level to which it is being programmed. One means of verifying the programming is to test conduction at a specific compare point. The cells that are verified to be sufficiently programmed are locked out, for example, by raising the bit line voltage from 0 to Vdd (e.g., 2.5 volts) to stop the programming process for those cells. In some cases, the number of pulses will be limited (e.g. 20 pulses) and if a given memory cell is not completely programmed by the last pulse, then an error is assumed. In some implementations, memory cells are erased (in blocks or other units) prior to programming. More information about programming can be found in U.S. patent application Ser. No. 10/379,608, titled “Self Boosting Technique,” filed on Mar. 5, 2003; and in U.S. patent application Ser. No. 10/629,068, titled “Detecting Over Programmed Memory,” filed on Jul. 29, 2003, both applications are incorporated herein by reference in their entirety.
FIG. 1 shows a program voltage signal Vpgm applied to the control gates of flash memory cells. The program voltage signal Vpgm includes a series of pulses that increase in magnitude over time. At the start of the program pulses, the bit lines (e.g. connected to the drain) of all cells that are to be programmed are grounded, thereby, creating a voltage difference of Vpgm−0 v from gate to channel. Once a cell reaches the targeted voltage (passing program verify), the respective bit line voltage is raised to Vdd so that the memory cell is in the program inhibit mode (e.g. program to that cell stops). Obviously, the faster programmed cells reach this condition earlier than the slower programmed cells. For example, FIG. 1 shows that the bit line voltage for a faster cell is raised to Vdd before the bit line voltage for a slower cell.
A multi-bit or multi-state flash memory cell is implemented by identifying multiple, distinct threshold voltage ranges within a device. Each distinct threshold voltage range corresponds to predetermined values for the set of data bits. The specific relationship between the data programmed into the memory cell and the threshold voltage levels of the cell depends upon the data encoding scheme adopted for the cells. For example, U.S. Pat. No. 6,222,762 and U.S. patent application Ser. No. 10/461,244, “Tracking Cells For A Memory System,” filed on Jun. 13, 2003, both of which are incorporated herein by reference in their entirety, describe various data encoding schemes for multi-state flash memory cells.
To achieve proper data storage for a multi-state cell, the multiple ranges of threshold voltage levels of the multi-state memory cell should be separated from each other by sufficient margin so that the level of the memory cell can be programmed or erased in an unambiguous manner. Additionally, a tight threshold voltage distribution is recommended. To achieve a tight threshold voltage distribution, small program steps typically have been used, thereby, programming the threshold voltage of the cells more slowly.
The natural threshold voltage distribution of a set of memory cells is the threshold voltage distribution obtained when the memory cells receive the same one or more pulses. FIG. 2 depicts the natural threshold voltage distribution W (natural VTH). The natural threshold voltage distribution reflects the natural physical and electrical variations of the large number of memory cells. There are many factors that contribute to the variations, such as active layer (cell width) size, channel length, tunnel oxide thickness, tunnel oxide local thinning, the shape of the floating gate, the inter-polysilicon ONO thickness as well as the source drain overlap area, etc. It is a challenge to make ever physically smaller and ever larger number of such cells identical. As devices get smaller and more states are used in multi-state cells, the natural threshold distribution widens and the need for tighter threshold distribution increases. As the natural threshold voltage distribution widens, more program steps are needed to obtain the required tight threshold voltage distribution. As more program steps are used, more time is needed for programming. From a consumer point of view, that means that the digital camera or other device using this memory storage operates more slowly. Thus, there is a need to increase programming speeds.